Skip to content

[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction #76210

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 4 commits into from
Dec 26, 2023
Merged

[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction #76210

merged 4 commits into from
Dec 26, 2023

Conversation

XinWang10
Copy link
Contributor

R16-R31 was added into GPRs in #70958,
This patch supports the encoding/decoding for promoted AMX-TILE instruction in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

@llvmbot llvmbot added backend:X86 mc Machine (object) code labels Dec 22, 2023
@llvmbot
Copy link
Member

llvmbot commented Dec 22, 2023 •
edited
Loading

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-mc

Author: None (XinWang10)

Changes

R16-R31 was added into GPRs in #70958,
This patch supports the encoding/decoding for promoted AMX-TILE instruction in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

Full diff: https://github.com/llvm/llvm-project/pull/76210.diff

16 Files Affected:

  • (modified) llvm/lib/Target/X86/X86InstrAMX.td (+48-16)
  • (added) llvm/test/MC/Disassembler/X86/apx/ldtilecfg.txt (+6)
  • (added) llvm/test/MC/Disassembler/X86/apx/sttilecfg.txt (+6)
  • (added) llvm/test/MC/Disassembler/X86/apx/tileloadd.txt (+6)
  • (added) llvm/test/MC/Disassembler/X86/apx/tileloaddt1.txt (+6)
  • (added) llvm/test/MC/Disassembler/X86/apx/tilestored.txt (+6)
  • (added) llvm/test/MC/X86/apx/ldtilecfg-att.s (+5)
  • (added) llvm/test/MC/X86/apx/ldtilecfg-intel.s (+5)
  • (added) llvm/test/MC/X86/apx/sttilecfg-att.s (+5)
  • (added) llvm/test/MC/X86/apx/sttilecfg-intel.s (+5)
  • (added) llvm/test/MC/X86/apx/tileloadd-att.s (+5)
  • (added) llvm/test/MC/X86/apx/tileloadd-intel.s (+5)
  • (added) llvm/test/MC/X86/apx/tileloaddt1-att.s (+5)
  • (added) llvm/test/MC/X86/apx/tileloaddt1-intel.s (+5)
  • (added) llvm/test/MC/X86/apx/tilestored-att.s (+5)
  • (added) llvm/test/MC/X86/apx/tilestored-intel.s (+5)
diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td
index 2dbb3e5ee3169c..007bde10222231 100644
--- a/llvm/lib/Target/X86/X86InstrAMX.td
+++ b/llvm/lib/Target/X86/X86InstrAMX.td
@@ -14,35 +14,67 @@
 //===----------------------------------------------------------------------===//
 // AMX instructions
 
-let Predicates = [HasAMXTILE, In64BitMode] in {
-  let SchedRW = [WriteSystem] in {
+let SchedRW = [WriteSystem] in {
+  let Predicates = [HasAMXTILE, NoEGPR, In64BitMode] in {
     let hasSideEffects = 1,
         Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
-    def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
-                       "ldtilecfg\t$src",
-                       [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS;
+    def LDTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                      "ldtilecfg\t$src",
+                      [(int_x86_ldtilecfg addr:$src)]>,
+                    VEX, T8PS;
     let hasSideEffects = 1 in
-    def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
-                       "sttilecfg\t$src",
-                       [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD;
+    def STTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                      "sttilecfg\t$src",
+                      [(int_x86_sttilecfg addr:$src)]>,
+                    VEX, T8PD;
     let mayLoad = 1 in
     def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
                       (ins sibmem:$src),
                       "tileloadd\t{$src, $dst|$dst, $src}", []>,
-                      VEX, T8XD;
+                    VEX, T8XD;
     let mayLoad = 1 in
     def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
                         (ins sibmem:$src),
                         "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
-                        VEX, T8PD;
-    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
-    def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
-                        "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
+                      VEX, T8PD;
     let mayStore = 1 in
     def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
                        (ins sibmem:$dst, TILE:$src),
                        "tilestored\t{$src, $dst|$dst, $src}", []>,
-                       VEX, T8XS;
+                      VEX, T8XS;
+  } // HasAMXTILE, NoEGPR
+  let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
+    let hasSideEffects = 1,
+        Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
+    def LDTILECFG_EVEX : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                           "ldtilecfg\t$src",
+                           [(int_x86_ldtilecfg addr:$src)]>,
+                         EVEX, NoCD8, T8PS;
+    let hasSideEffects = 1 in
+    def STTILECFG_EVEX : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
+                           "sttilecfg\t$src",
+                           [(int_x86_sttilecfg addr:$src)]>,
+                         EVEX, NoCD8, T8PD;
+    let mayLoad = 1 in
+    def TILELOADD_EVEX : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
+                           (ins sibmem:$src),
+                           "tileloadd\t{$src, $dst|$dst, $src}", []>,
+                         EVEX, NoCD8, T8XD;
+    let mayLoad = 1 in
+    def TILELOADDT1_EVEX : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
+                             (ins sibmem:$src),
+                             "tileloaddt1\t{$src, $dst|$dst, $src}", []>,
+                           EVEX, NoCD8, T8PD;
+    let mayStore = 1 in
+    def TILESTORED_EVEX : I<0x4b, MRMDestMemFSIB, (outs),
+                            (ins sibmem:$dst, TILE:$src),
+                            "tilestored\t{$src, $dst|$dst, $src}", []>,
+                          EVEX, NoCD8, T8XS;
+  } // HasAMXTILE, HasEGPR
+  let Predicates = [HasAMXTILE, In64BitMode] in {
+    let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
+    def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
+                        "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS;
     def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
                      "tilezero\t$dst", []>,
                      VEX, T8XD;
@@ -82,8 +114,8 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
       def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
                               [(int_x86_tilezero timm:$src)]>;
     }
-  } // SchedRW
-} // HasAMXTILE
+  } // HasAMXTILE
+} // SchedRW
 
 let Predicates = [HasAMXINT8, In64BitMode] in {
   let SchedRW = [WriteSystem] in {
diff --git a/llvm/test/MC/Disassembler/X86/apx/ldtilecfg.txt b/llvm/test/MC/Disassembler/X86/apx/ldtilecfg.txt
new file mode 100644
index 00000000000000..f5313b4026cbae
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/ldtilecfg.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   ldtilecfg	291(%r28,%r29,4)
+# INTEL: ldtilecfg	[r28 + 4*r29 + 291]
+0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/sttilecfg.txt b/llvm/test/MC/Disassembler/X86/apx/sttilecfg.txt
new file mode 100644
index 00000000000000..75afe12a907ef7
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/sttilecfg.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   sttilecfg	291(%r28,%r29,4)
+# INTEL: sttilecfg	[r28 + 4*r29 + 291]
+0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/tileloadd.txt b/llvm/test/MC/Disassembler/X86/apx/tileloadd.txt
new file mode 100644
index 00000000000000..029e0d30d3b835
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/tileloadd.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   tileloadd	291(%r28,%r29,4), %tmm6
+# INTEL: tileloadd	tmm6, [r28 + 4*r29 + 291]
+0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/tileloaddt1.txt b/llvm/test/MC/Disassembler/X86/apx/tileloaddt1.txt
new file mode 100644
index 00000000000000..a5ba5bb630e46f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/tileloaddt1.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   tileloaddt1	291(%r28,%r29,4), %tmm6
+# INTEL: tileloaddt1	tmm6, [r28 + 4*r29 + 291]
+0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/tilestored.txt b/llvm/test/MC/Disassembler/X86/apx/tilestored.txt
new file mode 100644
index 00000000000000..344dec34ef6015
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/tilestored.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   tilestored	%tmm6, 291(%r28,%r29,4)
+# INTEL: tilestored	[r28 + 4*r29 + 291], tmm6
+0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/ldtilecfg-att.s b/llvm/test/MC/X86/apx/ldtilecfg-att.s
new file mode 100644
index 00000000000000..a7e5991b5f9bea
--- /dev/null
+++ b/llvm/test/MC/X86/apx/ldtilecfg-att.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: ldtilecfg	291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
+         ldtilecfg	291(%r28,%r29,4)
diff --git a/llvm/test/MC/X86/apx/ldtilecfg-intel.s b/llvm/test/MC/X86/apx/ldtilecfg-intel.s
new file mode 100644
index 00000000000000..861af446f693af
--- /dev/null
+++ b/llvm/test/MC/X86/apx/ldtilecfg-intel.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: ldtilecfg	[r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
+         ldtilecfg	[r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/sttilecfg-att.s b/llvm/test/MC/X86/apx/sttilecfg-att.s
new file mode 100644
index 00000000000000..27253966b5af34
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sttilecfg-att.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: sttilecfg	291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
+         sttilecfg	291(%r28,%r29,4)
diff --git a/llvm/test/MC/X86/apx/sttilecfg-intel.s b/llvm/test/MC/X86/apx/sttilecfg-intel.s
new file mode 100644
index 00000000000000..27f47348107226
--- /dev/null
+++ b/llvm/test/MC/X86/apx/sttilecfg-intel.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: sttilecfg	[r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
+         sttilecfg	[r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/tileloadd-att.s b/llvm/test/MC/X86/apx/tileloadd-att.s
new file mode 100644
index 00000000000000..a31f2b7f3fd41e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tileloadd-att.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: tileloadd	291(%r28,%r29,4), %tmm6
+# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tileloadd	291(%r28,%r29,4), %tmm6
diff --git a/llvm/test/MC/X86/apx/tileloadd-intel.s b/llvm/test/MC/X86/apx/tileloadd-intel.s
new file mode 100644
index 00000000000000..48d7f124f8a332
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tileloadd-intel.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: tileloadd	tmm6, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tileloadd	tmm6, [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/tileloaddt1-att.s b/llvm/test/MC/X86/apx/tileloaddt1-att.s
new file mode 100644
index 00000000000000..55acafd6c15db4
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tileloaddt1-att.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: tileloaddt1	291(%r28,%r29,4), %tmm6
+# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tileloaddt1	291(%r28,%r29,4), %tmm6
diff --git a/llvm/test/MC/X86/apx/tileloaddt1-intel.s b/llvm/test/MC/X86/apx/tileloaddt1-intel.s
new file mode 100644
index 00000000000000..953ca49af64fc0
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tileloaddt1-intel.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: tileloaddt1	tmm6, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tileloaddt1	tmm6, [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/tilestored-att.s b/llvm/test/MC/X86/apx/tilestored-att.s
new file mode 100644
index 00000000000000..c832db3c8c8bd1
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tilestored-att.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: tilestored	%tmm6, 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tilestored	%tmm6, 291(%r28,%r29,4)
diff --git a/llvm/test/MC/X86/apx/tilestored-intel.s b/llvm/test/MC/X86/apx/tilestored-intel.s
new file mode 100644
index 00000000000000..c9f6a8ccc04923
--- /dev/null
+++ b/llvm/test/MC/X86/apx/tilestored-intel.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: tilestored	[r28 + 4*r29 + 291], tmm6
+# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
+         tilestored	[r28 + 4*r29 + 291], tmm6

phoebewang
phoebewang reviewed Dec 22, 2023
View reviewed changes
phoebewang
phoebewang approved these changes Dec 25, 2023
View reviewed changes
Copy link
Contributor

@phoebewang phoebewang left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM.

@XinWang10 XinWang10 merged commit 5c39b8d into llvm:main Dec 26, 2023
@XinWang10 XinWang10 mentioned this pull request Jan 2, 2024
Merged
XinWang10 added a commit that referenced this pull request Jan 4, 2024
@XinWang10
[NFC][X86] Reorg MC tests for APX promoted instrs (#76697)
ddf0096 
As suggested in #76210, this
patch re-organize the mc tests for apx promoted instrs, instr tests
within same cpuid would be listed in one test.
Also add explicit prefix {evex} tests and 8 displacement memory test,
promoted instrs need set No_CD8 to avoid AVX512 compress encoding.
@XinWang10 XinWang10 mentioned this pull request Jan 19, 2024
Merged
XinWang10 added a commit that referenced this pull request Jan 22, 2024
@XinWang10
[X86][APX]Support lowering for APX promoted AMX-TILE instructions (#7…
dd6fec5 
…8689)

The enc/dec of promoted AMX-TILE instructions have been supported in
#76210.
This patch support lowering for promoted AMX-TILE instructions and
integrate test to existing tests.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@KanRobert KanRobert KanRobert left review comments

@phoebewang phoebewang phoebewang approved these changes

@RKSimon RKSimon Awaiting requested review from RKSimon

@yubingex007-a11y yubingex007-a11y Awaiting requested review from yubingex007-a11y

Assignees
No one assigned
Labels
backend:X86 mc Machine (object) code
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@XinWang10 @llvmbot @phoebewang @KanRobert