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Issues: verilog-to-routing/vtr-verilog-to-routing
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draw critical path contour doesn't work with "crit path routing" drawing mode
#3062
opened May 20, 2025 by
w0lek
[Place] Unnecessary microoptimization in override_delay_model
Good First Issue
Good issues for new or first-time contributors
VPR
VPR FPGA Placement & Routing Tool
#3049
opened May 16, 2025 by
AmirhosseinPoolad
Clarify pack, place, route, analysis on vs. off reporting
#3039
opened May 14, 2025 by
vaughnb-cerebras
[STA] Post-Implementation STA Support for Dedicated Clock Network Modeling
#3027
opened May 7, 2025 by
AlexandreSinger
GUI not showing wires between connected CLBs despite highlighting
#3015
opened May 1, 2025 by
andrecavalcante
[Packer] Prepacker handling of pack pattern pins with net fanout > 1
#2996
opened Apr 22, 2025 by
amin1377
[Pack] Unneccesary mutation of the atom to clb lookup global context in packer
#2992
opened Apr 22, 2025 by
AmirhosseinPoolad
[Pack][Timing] Pre-Cluster Timing Analysis May Not Be Aware of Molecules
#2972
opened Apr 11, 2025 by
AlexandreSinger
Improve NoC arch tag documentation, and add ability to use equations in NoC tags
#2948
opened Mar 21, 2025 by
vaughnbetz
VTR standard benchmarks behave abnormally with '-parser system-verilog'
#2922
opened Mar 4, 2025 by
Junius00
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