[Infra] Cleaned Up Include Files in VPR Base Directory

Many include files in the base directory contained includes to other
headers which they do not use. This causes many CPP files to include way
more header files than they need, increasing the incremental build time.

This process needs to be done on the entire VTR repo, but I found that
the base directory was one of the biggest culprits of this and the
hardest to untangle.

Author: AlexandreSinger

libs/libarchfpga/src/arch_types.h

@@ -16,7 +16,7 @@
 #define TOKENS " \t\n"
 
 /* Value for UNDEFINED data */
-constexpr int UNDEFINED = -1;
+constexpr int ARCH_FPGA_UNDEFINED_VAL = -1;
 
 /* Maximum value for minimum channel width to avoid overflows of short data type.               */
 constexpr int MAX_CHANNEL_WIDTH = 8000;

libs/libarchfpga/src/arch_util.cpp

@@ -444,7 +444,7 @@ t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NA
     type.capacity = 0;
     type.num_drivers = 0;
     type.num_receivers = 0;
-    type.area = UNDEFINED;
+    type.area = ARCH_FPGA_UNDEFINED_VAL;
     type.switchblock_locations = vtr::Matrix<e_sb_type>({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL);
     type.switchblock_switch_overrides = vtr::Matrix<int>({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH);
     type.is_input_type = false;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2887,7 +2887,7 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu
                        "Unknown property %s for chan_width_distr x\n", Prop);
     }
 
-    chan->peak = get_attribute(Node, "peak", loc_data).as_float(UNDEFINED);
+    chan->peak = get_attribute(Node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL);
     chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0);
     chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0);
     chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0);
@@ -2994,7 +2994,7 @@ static void ProcessTileProps(pugi::xml_node Node,
     /* Load properties */
     PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1);
     PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1);
-    PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
+    PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL);
 
     if (atof(Prop) < 0) {
         archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
@@ -4264,8 +4264,8 @@ static std::vector<t_arch_switch_inf> ProcessSwitches(pugi::xml_node Parent,
 static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) {
     /* check if switch node has the Tdel property */
     bool has_Tdel_prop = false;
-    float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
-    if (Tdel_prop_value != UNDEFINED) {
+    float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL);
+    if (Tdel_prop_value != ARCH_FPGA_UNDEFINED_VAL) {
         has_Tdel_prop = true;
     }
 

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -464,7 +464,7 @@ size_t t_rr_graph_storage::count_rr_switches(
 
             if (arch_switch_inf[iswitch].fixed_Tdel()) {
                 //If delay is independent of fanin drop the unique fanin info
-                fanin = UNDEFINED;
+                fanin = ARCH_FPGA_UNDEFINED_VAL;
             }
 
             if (arch_switch_fanins[iswitch].count(fanin) == 0) {        //New fanin for this switch
@@ -482,7 +482,7 @@ size_t t_rr_graph_storage::count_rr_switches(
     for(size_t iswitch = 0; iswitch < arch_switch_counts.size(); ++iswitch) {
         if(arch_switch_fanins[iswitch].empty()){
             if(arch_switch_inf[iswitch].fixed_Tdel()){
-                arch_switch_fanins[iswitch][UNDEFINED] = num_rr_switches++;
+                arch_switch_fanins[iswitch][ARCH_FPGA_UNDEFINED_VAL] = num_rr_switches++;
             }
         }
     }
@@ -504,8 +504,8 @@ void t_rr_graph_storage::remap_rr_node_switch_indices(const t_arch_switch_fanin&
         int switch_index = edge_switch_[edge];
         int fanin = node_fan_in_[to_node];
 
-        if (switch_fanin[switch_index].count(UNDEFINED) == 1) {
-            fanin = UNDEFINED;
+        if (switch_fanin[switch_index].count(ARCH_FPGA_UNDEFINED_VAL) == 1) {
+            fanin = ARCH_FPGA_UNDEFINED_VAL;
         }
 
         auto itr = switch_fanin[switch_index].find(fanin);

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp

@@ -516,7 +516,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
     vtr::vector<RRIndexedDataId, std::vector<float>> switch_R_total(rr_indexed_data.size());
     vtr::vector<RRIndexedDataId, std::vector<float>> switch_T_total(rr_indexed_data.size());
     vtr::vector<RRIndexedDataId, std::vector<float>> switch_Cinternal_total(rr_indexed_data.size());
-    vtr::vector<RRIndexedDataId, short> switches_buffered(rr_indexed_data.size(), UNDEFINED);
+    vtr::vector<RRIndexedDataId, short> switches_buffered(rr_indexed_data.size(), ARCH_FPGA_UNDEFINED_VAL);
 
     /*
      * Walk through the RR graph and collect all R and C values of all the nodes,
@@ -542,7 +542,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
         double avg_switch_Cinternal = 0;
         int num_switches = 0;
         int num_shorts = 0;
-        short buffered = UNDEFINED;
+        short buffered = ARCH_FPGA_UNDEFINED_VAL;
         calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list);
 
         if (num_switches == 0) {
@@ -561,13 +561,13 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
         switch_R_total[cost_index].push_back(avg_switch_R);
         switch_T_total[cost_index].push_back(avg_switch_T);
         switch_Cinternal_total[cost_index].push_back(avg_switch_Cinternal);
-        if (buffered == UNDEFINED) {
+        if (buffered == ARCH_FPGA_UNDEFINED_VAL) {
             /* this segment does not have any outgoing edges to other general routing wires */
             continue;
         }
 
         /* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */
-        if (switches_buffered[cost_index] == UNDEFINED) {
+        if (switches_buffered[cost_index] == ARCH_FPGA_UNDEFINED_VAL) {
             switches_buffered[cost_index] = buffered;
         } else {
             if (switches_buffered[cost_index] != buffered) {
@@ -644,7 +644,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou
     avg_switch_Cinternal = 0;
     num_switches = 0;
     num_shorts = 0;
-    buffered = UNDEFINED;
+    buffered = ARCH_FPGA_UNDEFINED_VAL;
     for (const auto& edge : fan_in_list[node]) {
         /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
         if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) {
@@ -659,7 +659,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou
             avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel;
             avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal;
 
-            if (buffered == UNDEFINED) {
+            if (buffered == ARCH_FPGA_UNDEFINED_VAL) {
                 if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).buffered()) {
                     buffered = 1;
                 } else {

vpr/src/base/CheckArch.cpp

@@ -1,8 +1,6 @@
+#include "arch_util.h"
 #include "vpr_types.h"
 #include "vpr_error.h"
-#include "globals.h"
-#include "echo_files.h"
-#include "read_xml_arch_file.h"
 #include "CheckArch.h"
 
 /******** Function Prototypes ********/

vpr/src/base/CheckArch.h

@@ -1,6 +1,8 @@
 #ifndef CHECKARCH_H
 #define CHECKARCH_H
 
+#include "physical_types.h"
+
 void CheckArch(const t_arch& Arch);
 
 #endif

vpr/src/base/atom_lookup.h

@@ -2,15 +2,11 @@
 #define ATOM_LOOKUP_H
 #include "atom_lookup_fwd.h"
 
-#include <unordered_map>
-
-#include "vtr_bimap.h"
 #include "vtr_vector_map.h"
 #include "vtr_range.h"
 
 #include "atom_netlist_fwd.h"
 #include "clustered_netlist_fwd.h"
-#include "vpr_types.h"
 #include "tatum/TimingGraphFwd.hpp"
 
 #include "vtr_optional.h"

vpr/src/base/atom_netlist.cpp

@@ -2,6 +2,7 @@
 
 #include "atom_netlist.h"
 #include "logic_types.h"
+#include "netlist_utils.h"
 #include "vpr_error.h"
 #include "vtr_assert.h"
 

vpr/src/base/atom_netlist.h

@@ -68,7 +68,6 @@
 #include <vector>
 #include <unordered_map>
 
-#include "vtr_range.h"
 #include "vtr_logic.h"
 #include "vtr_vector_map.h"
 

vpr/src/base/clock_modeling.cpp

@@ -1,5 +1,6 @@
 #include "clock_modeling.h"
 #include "globals.h"
+#include "vpr_utils.h"
 #include "vtr_assert.h"
 
 void ClockModeling::treat_clock_pins_as_non_globals() {

vpr/src/base/clustered_netlist.cpp

@@ -2,8 +2,10 @@
 #include "globals.h"
 #include "logic_types.h"
 #include "physical_types_util.h"
+#include "vpr_utils.h"
 #include "vtr_assert.h"
 
+#include <regex>
 #include <utility>
 
 /**

vpr/src/base/clustered_netlist.h

@@ -106,9 +106,6 @@
  *
  */
 #include "vpr_types.h"
-#include "vpr_utils.h"
-
-#include "vtr_util.h"
 
 #include "netlist.h"
 #include "clustered_netlist_fwd.h"

vpr/src/base/constant_nets.cpp

@@ -1,5 +1,6 @@
 #include "constant_nets.h"
 
+#include "atom_netlist.h"
 #include "clustered_netlist.h"
 
 #include "vtr_assert.h"

vpr/src/base/constraints_load.h

@@ -1,11 +1,7 @@
 #ifndef CONSTRAINTS_LOAD_H_
 #define CONSTRAINTS_LOAD_H_
 
-#include "region.h"
-#include "partition.h"
-#include "partition_region.h"
 #include "user_place_constraints.h"
-#include "vtr_vector.h"
 
 ///@brief Used to print vpr's floorplanning constraints to an echo file "vpr_constraints.echo"
 void echo_constraints(char* filename, const UserPlaceConstraints& constraints);

vpr/src/base/echo_files.h

@@ -1,6 +1,8 @@
 #ifndef ECHO_FILES_H
 #define ECHO_FILES_H
 
+#include <string>
+
 enum e_echo_files {
 
     //Input netlist

vpr/src/base/netlist.h

@@ -417,13 +417,9 @@
 #include <vector>
 #include <unordered_map>
 #include "vtr_range.h"
-#include "vtr_logic.h"
 #include "vtr_vector_map.h"
 
-#include "logic_types.h"
-
 #include "netlist_fwd.h"
-#include "netlist_utils.h"
 
 //Forward declaration for private methods
 template<typename BlockId, typename PortId, typename PinId, typename NetId>

vpr/src/base/netlist.tpp

@@ -1,6 +1,7 @@
 #include <algorithm>
 #include <numeric>
 
+#include "netlist_utils.h"
 #include "vtr_assert.h"
 #include "vtr_log.h"
 #include "vpr_error.h"

vpr/src/base/partition.h

@@ -4,9 +4,8 @@
 #include <string>
 
 #include "vtr_strong_id.h"
-#include "region.h"
-#include "atom_netlist_fwd.h"
 #include "partition_region.h"
+
 /**
  * @file
  * @brief This file defines the data for a partition: a grouping of atoms that are constrained to a portion of an FPGA.

vpr/src/base/partition_region.h

@@ -2,7 +2,6 @@
 #define PARTITION_REGIONS_H
 
 #include "region.h"
-#include "atom_netlist_fwd.h"
 #include "vpr_types.h"
 
 /**

vpr/src/base/place_and_route.h

@@ -9,7 +9,6 @@
 #include "vpr_types.h"
 #include "timing_info.h"
 #include "RoutingDelayCalculator.h"
-#include "rr_graph.h"
 
 struct t_fmap_cell {
     int fs;         ///<at this fs

vpr/src/base/read_netlist.h

@@ -10,7 +10,9 @@
 #ifndef READ_NETLIST_H
 #define READ_NETLIST_H
 
-#include "vpr_types.h"
+#include "atom_netlist_fwd.h"
+#include "clustered_netlist_fwd.h"
+#include "physical_types.h"
 
 ClusteredNetlist read_netlist(const char* net_file,
                               const t_arch* arch,

vpr/src/base/read_options.h

@@ -1,7 +1,8 @@
 #ifndef READ_OPTIONS_H
 #define READ_OPTIONS_H
-#include "read_blif.h"
 
+#include "arch_types.h"
+#include "read_circuit.h"
 #include "vpr_types.h"
 #include "constant_nets.h"
 #include "ap_flow_enums.h"

vpr/src/base/read_place.h

@@ -6,6 +6,8 @@
 #include <string>
 
 class PlacerState;
+class BlkLocRegistry;
+class DeviceGrid;
 class ClusterBlockId;
 struct t_block_loc;
 

vpr/src/base/setup_noc.h

@@ -32,7 +32,6 @@
  */
 
 #include <string_view>
-#include <vector>
 
 #include "device_grid.h"
 #include "vpr_context.h"

vpr/src/base/stats.cpp

@@ -6,8 +6,10 @@
 #include <string>
 #include <iomanip>
 
+#include "physical_types.h"
 #include "physical_types_util.h"
 #include "route_tree.h"
+#include "vpr_utils.h"
 #include "vtr_assert.h"
 #include "vtr_log.h"
 #include "vtr_ndmatrix.h"

vpr/src/base/stats.h

@@ -1,9 +1,11 @@
 #pragma once
+
+#include <map>
 #include <vector>
-#include <limits>
-#include <algorithm>
-#include "vpr_types.h"
 #include "netlist.h"
+#include "rr_graph_type.h"
+
+class DeviceGrid;
 
 /**
  * @brief Prints out various statistics about the current routing.

vpr/src/base/user_route_constraints.cpp

@@ -1,4 +1,6 @@
 #include "user_route_constraints.h"
+#include <regex>
+#include "vpr_error.h"
 
 void UserRouteConstraints::add_route_constraint(std::string net_name, RoutingScheme route_scheme) {
     route_constraints_.insert({net_name, route_scheme});

vpr/src/base/user_route_constraints.h

@@ -2,9 +2,8 @@
 #define USER_ROUTE_CONSTRAINTS_H
 
 #include "clock_modeling.h"
-#include "vpr_error.h"
+#include <string>
 #include <unordered_map>
-#include <regex>
 
 /**
  * @brief This class specifies a routing scheme for a global net.

vpr/src/base/vpr_api.h

@@ -31,10 +31,6 @@
 #include "physical_types.h"
 #include "vpr_types.h"
 #include "read_options.h"
-#include "globals.h"
-#include "read_xml_arch_file.h"
-#include "vpr_utils.h"
-#include "place_macro.h"
 #include "timing_info_fwd.h"
 #include "echo_files.h"
 #include "RoutingDelayCalculator.h"

vpr/src/base/vpr_constraints_reader.cpp

@@ -1,3 +1,4 @@
+#include "constraints_load.h"
 #include "vpr_constraints_serializer.h"
 #include "vpr_constraints_uxsdcxx.h"
 

vpr/src/base/vpr_constraints_serializer.h

@@ -1,14 +1,12 @@
 #ifndef VPR_CONSTRAINTS_SERIALIZER_H_
 #define VPR_CONSTRAINTS_SERIALIZER_H_
 
+#include <regex>
 #include "region.h"
 #include "vpr_constraints.h"
 #include "partition.h"
 #include "partition_region.h"
-#include "echo_files.h"
-#include "constraints_load.h"
 #include "vtr_log.h"
-#include "vtr_error.h"
 #include "globals.h" //for the g_vpr_ctx
 #include "clock_modeling.h"