Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.
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Updated
Aug 13, 2024 - Verilog
Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.
digital systems
second project - Digital System
👾 My studies with Verilog and notions of digital systems.
Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.
Design and implementation of RISC-V processor with a single-cycle datapath and controller.
"Verilog HDL implementations of Hadamard and DCT (1D and 2D) transforms with modular design and complete simulations."
This repo contains Verilog Assignments of the course ES-204 Digital Systems held in II-Semester 2024 at IIT Gandhinagar - Prof. Joycee Mekie
Digital systems class at uni
Digital systems projects using languages such as verilog and vhdl and synthesis platforms such as quartus
Uma reprodução simplificada do jogo clássico de arcade asteroids, para sintetização em placa FPGA.
Proyecto Final: Sistemas digitales avanzados
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