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Add all memory barrier variants #50
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The Arm A-profile A64 Instruction Set Architecture[0] specifies many memory barrier variants. In the 2022-09 version of the document, they are in pages 348 and 351 for the DMB and DSB respectively. The cortex-a crate only supports SY, ISH and ISHST currently. Add the rest. [0] https://developer.arm.com/documentation/ddi0602/
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Thanks, will try to get it done over the weekend. |
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Brilliant, thanks! |
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The Arm A-profile A64 Instruction Set Architecture specifies many memory barrier variants. In the 2022-09 version of the document, they are in pages 348 and 351 for the DMB and DSB respectively.
The cortex-a crate only supports SY, ISH and ISHST currently. Add the rest.