Xtensa patches (16.x) (Do not merge, PR created for easier review only) #67
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Initial codegen support for simple ALU operations.
Constant Pool.
operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.
Implement lowering of dynamic_stackalloc, stacksave, stackrestore.
Also lower SHL, SRA, SRL with register operands.
patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.
Add support for llvm.{frameaddress,returnaddress} intrinsics.
Implement volatile load/store from/to volatile memory location.
scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.
Also implement User Registers class.
SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands.
The constant islands pass is always executed for large code model. Also currently is disabled support of the hardware loops for large code model, need to add support for hwloops in constant islands pass in future.
Do not use constant pool for aggregate or vector constant types, in such cases create global variable.
Set 32-bit alignmnet for i8 and i16 types.
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