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Jordi ChauziRomaric JODIN
Jordi Chauzi
authored and
Romaric JODIN
committed
dpu: llvm: MRAM pointer 64-bit access correctly uses SoftCache mechanism
Fix #5
1 parent 6c64033 commit 8d60a27

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2 files changed

+49
-6
lines changed

2 files changed

+49
-6
lines changed

llvm/lib/Target/DPU/DPUInstrInfo.td

+9-6
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,6 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
7272
return isOrEquivalentToAdd(N);
7373
}]>;
7474

75-
def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
76-
7775
class wram_load_frag<PatFrag base_load> : PatFrag<(ops node:$ptr), (base_load node:$ptr), [{
7876
return IsALoadFromAddrSpace(N, DPUADDR_SPACE::WRAM);
7977
}]>;
@@ -82,6 +80,8 @@ class wram_store_frag<PatFrag base_store> : PatFrag<(ops node:$val, node:$ptr),
8280
return IsAStoreToAddrSpace(N, DPUADDR_SPACE::WRAM);
8381
}]>;
8482

83+
def wram_loadi64 : PatFrag<(ops node:$ptr), (i64 (wram_load_frag<load> node:$ptr))>;
84+
8585
multiclass WramLoadXPat<ImmOperand LdTy, PatFrag LoadOp, DPUInstruction Inst> {
8686
def : Pat<(LdTy (wram_load_frag<LoadOp> SimpleRegOrCst:$ra)), (Inst SimpleRegOrCst:$ra, 0)>;
8787
def : Pat<(LdTy (wram_load_frag<LoadOp> AddrFI:$ra)), (Inst AddrFI:$ra, 0)>;
@@ -633,7 +633,7 @@ let usesCustomInserter = 1 in {
633633
def WRAM_LOAD_DOUBLErm : PseudoDPUInstruction<
634634
(outs GP64_REG:$dc), (ins MEMri24:$addr),
635635
"",
636-
[(set i64:$dc, (loadi64 ADDRESS_IN_STACK:$addr))]>;
636+
[(set i64:$dc, (wram_loadi64 ADDRESS_IN_STACK:$addr))]>;
637637

638638
def WRAM_LOAD_DOUBLE_ALIGNEDrm : PseudoDPUInstruction<
639639
(outs GP64_REG:$dc), (ins MEMri24:$addr),
@@ -700,8 +700,6 @@ let usesCustomInserter = 1 in {
700700
[(MramStore64 i64:$db, ADDRESS_IN_STACK:$addr)]
701701
>;
702702

703-
// TODO: MRAM LOAD DOUBLE
704-
705703
def MRAM_LOADmr : MRAM_LOAD_X_mr<mram_load>;
706704

707705
def MRAM_LOAD_U8mr : MRAM_LOAD_X_mr<mram_zextloadi8>;
@@ -715,4 +713,9 @@ let usesCustomInserter = 1 in {
715713
// Notice that this applies to "anyext from iXX, where XX is 8 or 16"
716714
def MRAM_LOAD_X8mr : MRAM_LOAD_X_mr<mram_extloadi8>;
717715
def MRAM_LOAD_X16mr : MRAM_LOAD_X_mr<mram_extloadi16>;
718-
}
716+
717+
def MRAM_LOAD_DOUBLEmr: PseudoDPUInstruction<
718+
(outs GP64_REG:$dc), (ins MEMri24:$addr),
719+
"",
720+
[(set i64:$dc, (mram_load ADDRESS_IN_STACK:$addr))]>;
721+
}

llvm/lib/Target/DPU/DPUTargetLowering.cpp

+40
Original file line numberDiff line numberDiff line change
@@ -2312,6 +2312,44 @@ EmitMramSubLoadWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB,
23122312
return BB;
23132313
}
23142314

2315+
static MachineBasicBlock *
2316+
EmitMramLoadDoubleWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) {
2317+
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
2318+
DebugLoc dl = MI.getDebugLoc();
2319+
MachineFunction *F = BB->getParent();
2320+
2321+
MachineRegisterInfo &RI = F->getRegInfo();
2322+
unsigned WramCacheAddrReg = RI.createVirtualRegister(&DPU::GP_REGRegClass);
2323+
unsigned MramAddrReg = RI.createVirtualRegister(&DPU::GP_REGRegClass);
2324+
2325+
// todo __sw_cache_buffer should have abstract representation
2326+
2327+
BuildMI(*BB, MI, dl, TII.get(DPU::ADDrri), WramCacheAddrReg)
2328+
.addReg(DPU::ID8)
2329+
.addExternalSymbol("__sw_cache_buffer");
2330+
2331+
if (MI.getOperand(2).getImm() == 0) {
2332+
BuildMI(*BB, MI, dl, TII.get(DPU::COPY), MramAddrReg).add(MI.getOperand(1));
2333+
} else {
2334+
BuildMI(*BB, MI, dl, TII.get(DPU::ADDrri), MramAddrReg)
2335+
.add(MI.getOperand(1))
2336+
.add(MI.getOperand(2));
2337+
}
2338+
2339+
BuildMI(*BB, MI, dl, TII.get(DPU::LDMArri))
2340+
.addReg(WramCacheAddrReg)
2341+
.addReg(MramAddrReg)
2342+
.addImm(0);
2343+
2344+
BuildMI(*BB, MI, dl, TII.get(DPU::LDrri))
2345+
.add(MI.getOperand(0))
2346+
.addReg(WramCacheAddrReg)
2347+
.addImm(0);
2348+
2349+
MI.eraseFromParent(); // The pseudo instruction is gone now.
2350+
return BB;
2351+
}
2352+
23152353
static MachineBasicBlock *
23162354
EmitAlignedStoreWramDoubleRegisterWithCustomInserter(MachineInstr &MI,
23172355
MachineBasicBlock *BB) {
@@ -3482,6 +3520,8 @@ DPUTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
34823520
case DPU::MRAM_LOAD_U32mr:
34833521
case DPU::MRAM_LOADmr:
34843522
return EmitMramSubLoadWithCustomInserter(MI, BB, 4, DPU::LWrri);
3523+
case DPU::MRAM_LOAD_DOUBLEmr:
3524+
return EmitMramLoadDoubleWithCustomInserter(MI, BB);
34853525
case DPU::WRAM_STORE_DOUBLErm:
34863526
return EmitUnalignedStoreWramDoubleRegisterWithCustomInserter(MI, BB);
34873527
case DPU::WRAM_STORE_DOUBLE_ALIGNEDrm:

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