wip: I fixed all issues reported with -verify-machineinstrs, need LARGE cleanup now ...

While at it, I implemented some quick optimization.

- Implemented `(1 << n) - 1` == `lslx lneg n`
#9

- Moved some 64-bit operation earlier in the pipeline,
from ResolveMacroInstrPass to expandPostRA.
I tried even earlier, but SUBC is not well defined and get moved around during MergeSink
for critical edge split. The computation is then wrong because require to be packed for the
particular use I identified.
I leave my experiment here. I will check to fully define it and move it preRA, or will leave it
like that again for a while, fulfilling my other duty.

- Fixed a few easy Def/Use when BuildMI

- Fixed lose of MachineInstr correctness
Our arithmetic+comp+branch was destroyed during analyzeBranch/removeBranch/insertBranch

- temporarily removed fusion of any instruction + JUMPi in MergeComboInstr
The problem is that at this stage (PreEmit):
- machine CFG is done.
- JUMPi is unconditional jump
- arithmetic + cond + branch; with cond as True/False is conditional
-- even if we know that cond with true/false is unconditional, the instruction have the
-- property of being conditional by its definition.
---- To fix that, I will create other PseudoInstruction to have them set correctly.
---- Also, if those arith+cond+branch do have pattern, maybe they could be selected far earlier
---- and the machine CFG would be correctly formed at the first place probably.

- issue with ThinLTO fixed
-- some code construction ended up in SELECTrr, which is not common for us
---- this is lowered to TmpJcc
---- and TmpJcc is kind of wrong
------ and finally, MergeComboInstr was combining even more wrong.
--> I removed TmpJcc, and use simply our well defined JEQrii

- issue whith ThinLTO fixed
-- another was present but undetected on Release build
-- we use multiple address spacees (IRAM, WRAM, MRAM)
-- there was an assertion with ThinLTO when populating GV out of multiple modules
---- it's fixed in llvm13, but we are on llvm12
------ I reproduced the patch (not cherry-picked) llvm@60c60dd
------ just for now. will do that correctly when cleaning up
------- so when I will upgrade our LLVM, it will be mergeable easily

Author: wwolff42

llvm/lib/CodeGen/MachineSink.cpp

@@ -1103,23 +1103,51 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
 bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
                                      AllSuccsCache &AllSuccessors) {
   // Don't sink instructions that the target prefers not to sink.
-  if (!TII->shouldSink(MI))
+  if (!TII->shouldSink(MI)) {
+    // LLVM_DEBUG({
+    // 	dbgs() << "shouldSink false "; MI.dump();
+    //   });
     return false;
-
+  }
+  
   // Check if it's safe to move the instruction.
-  if (!MI.isSafeToMove(AA, SawStore))
+  if (!MI.isSafeToMove(AA, SawStore)) {
+    // LLVM_DEBUG({
+    // 	dbgs() << "not safe "; MI.dump();
+    // 	dbgs() << "mayStore(): " << MI.mayStore() << "\n";
+    // 	dbgs() << "mayLoad(): " << MI.mayLoad() << "\n";
+    // 	dbgs() << "isCall(): " << MI.isCall() << "\n";
+    // 	dbgs() << "isPHI(): " << MI.isPHI() << "\n";
+    // 	dbgs() << "hasOrderedMemoryRef(): " << MI.hasOrderedMemoryRef() << "\n";
+    // 	dbgs() << "isPosition(): " << MI.isPosition() << "\n";
+    // 	dbgs() << "isDebugInstr(): " << MI.isDebugInstr() << "\n";
+    // 	dbgs() << "isTerminator(): " << MI.isTerminator() << "\n";
+    // 	dbgs() << "mayRaiseFPException(): " << MI.mayRaiseFPException() << "\n";
+    // 	dbgs() << "hasUnmodeledSideEffects(): " << MI.hasUnmodeledSideEffects() << "\n";
+    // 	dbgs() << "isDereferenceableInvariantLoad(AA): " << MI.isDereferenceableInvariantLoad(AA) << "\n";
+    // 	dbgs() << "SawStore: " << SawStore << "\n";
+    //   });
     return false;
-
+  }
+  
   // Convergent operations may not be made control-dependent on additional
   // values.
-  if (MI.isConvergent())
+  if (MI.isConvergent()) {
+    // LLVM_DEBUG({
+    // 	dbgs() << "isconvergent "; MI.dump();
+    //   });
     return false;
-
+  }
+  
   // Don't break implicit null checks.  This is a performance heuristic, and not
   // required for correctness.
-  if (SinkingPreventsImplicitNullCheck(MI, TII, TRI))
+  if (SinkingPreventsImplicitNullCheck(MI, TII, TRI)) {
+    LLVM_DEBUG({
+	dbgs() << "nullcheck "; MI.dump();
+      });
     return false;
-
+  }
+  
   // FIXME: This should include support for sinking instructions within the
   // block they are currently in to shorten the live ranges.  We often get
   // instructions sunk into the top of a large block, but it would be better to
@@ -1134,9 +1162,12 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
       FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge, AllSuccessors);
 
   // If there are no outputs, it must have side-effects.
-  if (!SuccToSinkTo)
+  if (!SuccToSinkTo) {
+    // LLVM_DEBUG({
+    // 	dbgs() << "no succ "; MI.dump();
+    //   });
     return false;
-
+  }
   // If the instruction to move defines a dead physical register which is live
   // when leaving the basic block, don't move it because it could turn into a
   // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
@@ -1146,8 +1177,12 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
     Register Reg = MO.getReg();
     if (Reg == 0 || !Register::isPhysicalRegister(Reg))
       continue;
-    if (SuccToSinkTo->isLiveIn(Reg))
+    if (SuccToSinkTo->isLiveIn(Reg)) {
+      // LLVM_DEBUG({
+      // 	  dbgs() << "zombie "; MI.dump();
+      // 	});
       return false;
+    }
   }
 
   LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);