[RISCV] Don't custom legalize vXf16 SPLAT_VECTOR with Zvfhmin without Zfhmin.

Marking SPLAT_VECTOR as Custom enables generic DAGCombine to turn
BUILD_VECTOR into SPLAT_VECTOR. We need to custom type legalize BUILD_VECTOR
without Zfhmin since we don't have the scalar f16 type. If we allow
SPLAT_VECTOR to be formed, we'll need to custom type legalize it too.

Easiest fix is to only enable SPLAT_VECTOR with Zvfhmin+Zfhmin. There's
still an issue that we need to properly support BUILD_VECTOR with Zvfhmin+Zfhmin.

Should fix the new case reported in #97849.

I've also changed the predicates to Zfhmin instead of ZfhminOrZhinxmin
since Zhinx isn't compatible with Zvfhmin.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -1078,7 +1078,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
                             ISD::EXTRACT_SUBVECTOR},
                            VT, Custom);
-        if (Subtarget.hasStdExtZfhminOrZhinxmin())
+        if (Subtarget.hasStdExtZfhmin())
           setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
         // load/store
         setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
@@ -1327,12 +1327,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                               ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
                              VT, Custom);
           setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
-          // FIXME: We should prefer BUILD_VECTOR over SPLAT_VECTOR.
-          setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
-          // We need to custom legalize f16 build vectors if Zfhmin isn't
-          // available.
-          if (!Subtarget.hasStdExtZfhminOrZhinxmin())
+          if (Subtarget.hasStdExtZfhmin()) {
+            // FIXME: We should prefer BUILD_VECTOR over SPLAT_VECTOR.
+            setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
+          } else {
+            // We need to custom legalize f16 build vectors if Zfhmin isn't
+            // available.
             setOperationAction(ISD::BUILD_VECTOR, MVT::f16, Custom);
+          }
           MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
           // Don't promote f16 vector operations to f32 if f32 vector type is
           // not legal.
@@ -4001,7 +4003,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 
   // If we don't have scalar f16, we need to bitcast to an i16 vector.
   if (VT.getVectorElementType() == MVT::f16 &&
-      !Subtarget.hasStdExtZfhminOrZhinxmin())
+      !Subtarget.hasStdExtZfhmin())
     return lowerBUILD_VECTORvXf16(Op, DAG);
 
   if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

@@ -1,14 +1,30 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFH
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN
 
 define void @splat_v8f16(ptr %x, half %y) {
-; CHECK-LABEL: splat_v8f16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    vse16.v v8, (a0)
-; CHECK-NEXT:    ret
+; CHECK-RV32-LABEL: splat_v8f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-RV32-NEXT:    vfmv.v.f v8, fa0
+; CHECK-RV32-NEXT:    vse16.v v8, (a0)
+; CHECK-RV32-NEXT:    ret
+;
+; RV64-ZVFH-LABEL: splat_v8f16:
+; RV64-ZVFH:       # %bb.0:
+; RV64-ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV64-ZVFH-NEXT:    vfmv.v.f v8, fa0
+; RV64-ZVFH-NEXT:    vse16.v v8, (a0)
+; RV64-ZVFH-NEXT:    ret
+;
+; RV64-ZVFHMIN-LABEL: splat_v8f16:
+; RV64-ZVFHMIN:       # %bb.0:
+; RV64-ZVFHMIN-NEXT:    fmv.x.w a1, fa0
+; RV64-ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV64-ZVFHMIN-NEXT:    vmv.v.x v8, a1
+; RV64-ZVFHMIN-NEXT:    vse16.v v8, (a0)
+; RV64-ZVFHMIN-NEXT:    ret
   %a = insertelement <8 x half> poison, half %y, i32 0
   %b = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer
   store <8 x half> %b, ptr %x
@@ -42,12 +58,27 @@ define void @splat_v2f64(ptr %x, double %y) {
 }
 
 define void @splat_16f16(ptr %x, half %y) {
-; CHECK-LABEL: splat_16f16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    vse16.v v8, (a0)
-; CHECK-NEXT:    ret
+; CHECK-RV32-LABEL: splat_16f16:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-RV32-NEXT:    vfmv.v.f v8, fa0
+; CHECK-RV32-NEXT:    vse16.v v8, (a0)
+; CHECK-RV32-NEXT:    ret
+;
+; RV64-ZVFH-LABEL: splat_16f16:
+; RV64-ZVFH:       # %bb.0:
+; RV64-ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; RV64-ZVFH-NEXT:    vfmv.v.f v8, fa0
+; RV64-ZVFH-NEXT:    vse16.v v8, (a0)
+; RV64-ZVFH-NEXT:    ret
+;
+; RV64-ZVFHMIN-LABEL: splat_16f16:
+; RV64-ZVFHMIN:       # %bb.0:
+; RV64-ZVFHMIN-NEXT:    fmv.x.w a1, fa0
+; RV64-ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
+; RV64-ZVFHMIN-NEXT:    vmv.v.x v8, a1
+; RV64-ZVFHMIN-NEXT:    vse16.v v8, (a0)
+; RV64-ZVFHMIN-NEXT:    ret
   %a = insertelement <16 x half> poison, half %y, i32 0
   %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer
   store <16 x half> %b, ptr %x