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alexey-bataevalexey-bataev
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[SLP][NFC]Add a test with potential segmented loads, recognized as strided
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‎llvm/test/Transforms/SLPVectorizer/RISCV/segmented-loads-simple.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -S -passes=slp-vectorizer < %s -mtriple=riscv64-unknown-linux -mattr=+v | FileCheck %s
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define i32 @sum_of_abs_stride_2(ptr noalias %a, ptr noalias %b) {
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; CHECK-LABEL: define i32 @sum_of_abs_stride_2
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; CHECK-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i64(ptr align 1 [[A]], i64 2, <8 x i1> splat (i1 true), i32 8)
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
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; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]])
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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entry:
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%0 = load i8, ptr %a, align 1
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%spec.select.i = tail call i8 @llvm.abs.i8(i8 %0, i1 false)
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%conv = sext i8 %spec.select.i to i32
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%arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 2
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%1 = load i8, ptr %arrayidx.1, align 1
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%spec.select.i.1 = tail call i8 @llvm.abs.i8(i8 %1, i1 false)
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%conv.1 = sext i8 %spec.select.i.1 to i32
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%add.1 = add nsw i32 %conv, %conv.1
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%arrayidx.2 = getelementptr inbounds i8, ptr %a, i64 4
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%2 = load i8, ptr %arrayidx.2, align 1
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%spec.select.i.2 = tail call i8 @llvm.abs.i8(i8 %2, i1 false)
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%conv.2 = sext i8 %spec.select.i.2 to i32
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%add.2 = add nsw i32 %add.1, %conv.2
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%arrayidx.3 = getelementptr inbounds i8, ptr %a, i64 6
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%3 = load i8, ptr %arrayidx.3, align 1
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%spec.select.i.3 = tail call i8 @llvm.abs.i8(i8 %3, i1 false)
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%conv.3 = sext i8 %spec.select.i.3 to i32
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%add.3 = add nsw i32 %add.2, %conv.3
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%arrayidx.4 = getelementptr inbounds i8, ptr %a, i64 8
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%4 = load i8, ptr %arrayidx.4, align 1
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%spec.select.i.4 = tail call i8 @llvm.abs.i8(i8 %4, i1 false)
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%conv.4 = sext i8 %spec.select.i.4 to i32
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%add.4 = add nsw i32 %add.3, %conv.4
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%arrayidx.5 = getelementptr inbounds i8, ptr %a, i64 10
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%5 = load i8, ptr %arrayidx.5, align 1
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%spec.select.i.5 = tail call i8 @llvm.abs.i8(i8 %5, i1 false)
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%conv.5 = sext i8 %spec.select.i.5 to i32
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%add.5 = add nsw i32 %add.4, %conv.5
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%arrayidx.6 = getelementptr inbounds i8, ptr %a, i64 12
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%6 = load i8, ptr %arrayidx.6, align 1
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%spec.select.i.6 = tail call i8 @llvm.abs.i8(i8 %6, i1 false)
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%conv.6 = sext i8 %spec.select.i.6 to i32
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%add.6 = add nsw i32 %add.5, %conv.6
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%arrayidx.7 = getelementptr inbounds i8, ptr %a, i64 14
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%7 = load i8, ptr %arrayidx.7, align 1
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%spec.select.i.7 = tail call i8 @llvm.abs.i8(i8 %7, i1 false)
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%conv.7 = sext i8 %spec.select.i.7 to i32
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%add.7 = add nsw i32 %add.6, %conv.7
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ret i32 %add.7
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}
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define i32 @sum_of_abs_stride_3(ptr noalias %a, ptr noalias %b) {
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; CHECK-LABEL: define i32 @sum_of_abs_stride_3
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; CHECK-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = call <8 x i8> @llvm.experimental.vp.strided.load.v8i8.p0.i64(ptr align 1 [[A]], i64 3, <8 x i1> splat (i1 true), i32 8)
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
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; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]])
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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entry:
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%0 = load i8, ptr %a, align 1
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%spec.select.i = tail call i8 @llvm.abs.i8(i8 %0, i1 false)
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%conv = sext i8 %spec.select.i to i32
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%arrayidx.1 = getelementptr inbounds i8, ptr %a, i64 3
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%1 = load i8, ptr %arrayidx.1, align 1
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%spec.select.i.1 = tail call i8 @llvm.abs.i8(i8 %1, i1 false)
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%conv.1 = sext i8 %spec.select.i.1 to i32
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%add.1 = add nsw i32 %conv, %conv.1
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%arrayidx.2 = getelementptr inbounds i8, ptr %a, i64 6
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%2 = load i8, ptr %arrayidx.2, align 1
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%spec.select.i.2 = tail call i8 @llvm.abs.i8(i8 %2, i1 false)
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%conv.2 = sext i8 %spec.select.i.2 to i32
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%add.2 = add nsw i32 %add.1, %conv.2
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%arrayidx.3 = getelementptr inbounds i8, ptr %a, i64 9
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%3 = load i8, ptr %arrayidx.3, align 1
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%spec.select.i.3 = tail call i8 @llvm.abs.i8(i8 %3, i1 false)
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%conv.3 = sext i8 %spec.select.i.3 to i32
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%add.3 = add nsw i32 %add.2, %conv.3
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%arrayidx.4 = getelementptr inbounds i8, ptr %a, i64 12
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%4 = load i8, ptr %arrayidx.4, align 1
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%spec.select.i.4 = tail call i8 @llvm.abs.i8(i8 %4, i1 false)
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%conv.4 = sext i8 %spec.select.i.4 to i32
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%add.4 = add nsw i32 %add.3, %conv.4
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%arrayidx.5 = getelementptr inbounds i8, ptr %a, i64 15
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%5 = load i8, ptr %arrayidx.5, align 1
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%spec.select.i.5 = tail call i8 @llvm.abs.i8(i8 %5, i1 false)
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%conv.5 = sext i8 %spec.select.i.5 to i32
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%add.5 = add nsw i32 %add.4, %conv.5
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%arrayidx.6 = getelementptr inbounds i8, ptr %a, i64 18
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%6 = load i8, ptr %arrayidx.6, align 1
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%spec.select.i.6 = tail call i8 @llvm.abs.i8(i8 %6, i1 false)
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%conv.6 = sext i8 %spec.select.i.6 to i32
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%add.6 = add nsw i32 %add.5, %conv.6
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%arrayidx.7 = getelementptr inbounds i8, ptr %a, i64 21
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%7 = load i8, ptr %arrayidx.7, align 1
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%spec.select.i.7 = tail call i8 @llvm.abs.i8(i8 %7, i1 false)
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%conv.7 = sext i8 %spec.select.i.7 to i32
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%add.7 = add nsw i32 %add.6, %conv.7
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ret i32 %add.7
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}
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declare i8 @llvm.abs.i8(i8, i1 immarg)

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