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Remove FLASH cache mentioning for bits 3 and 4 of dport0 3FF00024 register.
Document high 32K of IRAM region and corresponding 0x3ff00024 control bits
add internal i2c controller
Tested with JTAG debugger that there is 64K IRAM, not 32K + 0x308. Tested that regions above it are not writable.
Update memory map for RTC and OTA IRAM from sven337 over IRC.
Add FLASH mapping to memory details
Add note about UART divisor.
add SPI controller registers
Add 3FF00014h from looking at IoT_Demo/ssl/app/espconn_ssl.c
Fix iram1 size
Update SPI Flash area info.
Document SPI mapping hardware properties.
Updated Memory Map (markdown)
Add iomux pin register diagram
Add MMIO registers from headers. Only uart0 and uart1 confirmed in code.
Say that MDK is probably unused without OTA
Redo memory map after doing some actual probing.
Add non-OTA SPI Flash layout as it is still supported.
Update SPI memory map to OTA.
Add SPI memory map
Add memory map page with info from forum post, linker scripts and xt2000-rt/memmap.xmm