Skip to content

Commit 63ca22a

Browse files
Dan Gohmanalexcrichton
Dan Gohman
authored and
alexcrichton
committed
[WebAssembly] Fix trapping behavior in fptosi/fptoui.
This adds code to protect WebAssembly's `trunc_s` family of opcodes from values outside their domain. Even though such conversions have full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do not, and only return undef. This also implements the proposed non-trapping float-to-int conversion feature and uses that instead when available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319128 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 482a0b1 commit 63ca22a

10 files changed

+402
-27
lines changed

‎lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp

+7-2
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,13 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
6060
uint64_t Start = OS.tell();
6161

6262
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
63-
assert(Binary < UINT8_MAX && "Multi-byte opcodes not supported yet");
64-
OS << uint8_t(Binary);
63+
if (Binary <= UINT8_MAX) {
64+
OS << uint8_t(Binary);
65+
} else {
66+
assert(Binary <= UINT16_MAX && "Several-byte opcodes not supported yet");
67+
OS << uint8_t(Binary >> 8)
68+
<< uint8_t(Binary);
69+
}
6570

6671
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
6772
for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {

‎lib/Target/WebAssembly/WebAssembly.td

+4
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,10 @@ include "llvm/Target/Target.td"
2525

2626
def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
2727
"Enable 128-bit SIMD">;
28+
def FeatureNontrappingFPToInt :
29+
SubtargetFeature<"nontrapping-fptoint",
30+
"HasNontrappingFPToInt", "true",
31+
"Enable non-trapping float-to-int conversion operators">;
2832

2933
//===----------------------------------------------------------------------===//
3034
// Architectures.

‎lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

+129
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "WebAssemblyTargetMachine.h"
2020
#include "llvm/CodeGen/Analysis.h"
2121
#include "llvm/CodeGen/CallingConvLower.h"
22+
#include "llvm/CodeGen/MachineInstrBuilder.h"
2223
#include "llvm/CodeGen/MachineJumpTableInfo.h"
2324
#include "llvm/CodeGen/MachineRegisterInfo.h"
2425
#include "llvm/CodeGen/SelectionDAG.h"
@@ -173,6 +174,134 @@ MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
173174
return Result;
174175
}
175176

177+
// Lower an fp-to-int conversion operator from the LLVM opcode, which has an
178+
// undefined result on invalid/overflow, to the WebAssembly opcode, which
179+
// traps on invalid/overflow.
180+
static MachineBasicBlock *
181+
LowerFPToInt(
182+
MachineInstr &MI,
183+
DebugLoc DL,
184+
MachineBasicBlock *BB,
185+
const TargetInstrInfo &TII,
186+
bool IsUnsigned,
187+
bool Int64,
188+
bool Float64,
189+
unsigned LoweredOpcode
190+
) {
191+
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
192+
193+
unsigned OutReg = MI.getOperand(0).getReg();
194+
unsigned InReg = MI.getOperand(1).getReg();
195+
196+
unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
197+
unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
198+
unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
199+
unsigned IConst = Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
200+
int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
201+
int64_t Substitute = IsUnsigned ? 0 : Limit;
202+
double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
203+
auto &Context = BB->getParent()->getFunction()->getContext();
204+
Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context);
205+
206+
const BasicBlock *LLVM_BB = BB->getBasicBlock();
207+
MachineFunction *F = BB->getParent();
208+
MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(LLVM_BB);
209+
MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
210+
MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(LLVM_BB);
211+
212+
MachineFunction::iterator It = ++BB->getIterator();
213+
F->insert(It, FalseMBB);
214+
F->insert(It, TrueMBB);
215+
F->insert(It, DoneMBB);
216+
217+
// Transfer the remainder of BB and its successor edges to DoneMBB.
218+
DoneMBB->splice(DoneMBB->begin(), BB,
219+
std::next(MachineBasicBlock::iterator(MI)),
220+
BB->end());
221+
DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
222+
223+
BB->addSuccessor(TrueMBB);
224+
BB->addSuccessor(FalseMBB);
225+
TrueMBB->addSuccessor(DoneMBB);
226+
FalseMBB->addSuccessor(DoneMBB);
227+
228+
unsigned Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
229+
Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
230+
Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
231+
Tmp2 = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
232+
Tmp3 = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
233+
Tmp4 = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
234+
235+
MI.eraseFromParent();
236+
if (IsUnsigned) {
237+
Tmp0 = InReg;
238+
} else {
239+
BuildMI(BB, DL, TII.get(Abs), Tmp0)
240+
.addReg(InReg);
241+
}
242+
BuildMI(BB, DL, TII.get(FConst), Tmp1)
243+
.addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
244+
BuildMI(BB, DL, TII.get(LT), Tmp2)
245+
.addReg(Tmp0)
246+
.addReg(Tmp1);
247+
BuildMI(BB, DL, TII.get(WebAssembly::BR_IF))
248+
.addMBB(TrueMBB)
249+
.addReg(Tmp2);
250+
251+
BuildMI(FalseMBB, DL, TII.get(IConst), Tmp3)
252+
.addImm(Substitute);
253+
BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR))
254+
.addMBB(DoneMBB);
255+
BuildMI(TrueMBB, DL, TII.get(LoweredOpcode), Tmp4)
256+
.addReg(InReg);
257+
258+
BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
259+
.addReg(Tmp3)
260+
.addMBB(FalseMBB)
261+
.addReg(Tmp4)
262+
.addMBB(TrueMBB);
263+
264+
return DoneMBB;
265+
}
266+
267+
MachineBasicBlock *
268+
WebAssemblyTargetLowering::EmitInstrWithCustomInserter(
269+
MachineInstr &MI,
270+
MachineBasicBlock *BB
271+
) const {
272+
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
273+
DebugLoc DL = MI.getDebugLoc();
274+
275+
switch (MI.getOpcode()) {
276+
default: llvm_unreachable("Unexpected instr type to insert");
277+
case WebAssembly::FP_TO_SINT_I32_F32:
278+
return LowerFPToInt(MI, DL, BB, TII, false, false, false,
279+
WebAssembly::I32_TRUNC_S_F32);
280+
case WebAssembly::FP_TO_UINT_I32_F32:
281+
return LowerFPToInt(MI, DL, BB, TII, true, false, false,
282+
WebAssembly::I32_TRUNC_U_F32);
283+
case WebAssembly::FP_TO_SINT_I64_F32:
284+
return LowerFPToInt(MI, DL, BB, TII, false, true, false,
285+
WebAssembly::I64_TRUNC_S_F32);
286+
case WebAssembly::FP_TO_UINT_I64_F32:
287+
return LowerFPToInt(MI, DL, BB, TII, true, true, false,
288+
WebAssembly::I64_TRUNC_U_F32);
289+
case WebAssembly::FP_TO_SINT_I32_F64:
290+
return LowerFPToInt(MI, DL, BB, TII, false, false, true,
291+
WebAssembly::I32_TRUNC_S_F64);
292+
case WebAssembly::FP_TO_UINT_I32_F64:
293+
return LowerFPToInt(MI, DL, BB, TII, true, false, true,
294+
WebAssembly::I32_TRUNC_U_F64);
295+
case WebAssembly::FP_TO_SINT_I64_F64:
296+
return LowerFPToInt(MI, DL, BB, TII, false, true, true,
297+
WebAssembly::I64_TRUNC_S_F64);
298+
case WebAssembly::FP_TO_UINT_I64_F64:
299+
return LowerFPToInt(MI, DL, BB, TII, true, true, true,
300+
WebAssembly::I64_TRUNC_U_F64);
301+
llvm_unreachable("Unexpected instruction to emit with custom inserter");
302+
}
303+
}
304+
176305
const char *WebAssemblyTargetLowering::getTargetNodeName(
177306
unsigned Opcode) const {
178307
switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {

‎lib/Target/WebAssembly/WebAssemblyISelLowering.h

+3
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,9 @@ class WebAssemblyTargetLowering final : public TargetLowering {
4848
const TargetLibraryInfo *LibInfo) const override;
4949
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
5050
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
51+
MachineBasicBlock *
52+
EmitInstrWithCustomInserter(MachineInstr &MI,
53+
MachineBasicBlock *MBB) const override;
5154
const char *getTargetNodeName(unsigned Opcode) const override;
5255
std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
5356
const TargetRegisterInfo *TRI, StringRef Constraint,

‎lib/Target/WebAssembly/WebAssemblyInstrConv.td

+72-16
Original file line numberDiff line numberDiff line change
@@ -35,32 +35,88 @@ def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
3535

3636
let Defs = [ARGUMENTS] in {
3737

38+
// Conversion from floating point to integer instructions which don't trap on
39+
// overflow or invalid.
40+
def I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src),
41+
[(set I32:$dst, (fp_to_sint F32:$src))],
42+
"i32.trunc_s:sat/f32\t$dst, $src", 0xfc00>,
43+
Requires<[HasNontrappingFPToInt]>;
44+
def I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src),
45+
[(set I32:$dst, (fp_to_uint F32:$src))],
46+
"i32.trunc_u:sat/f32\t$dst, $src", 0xfc01>,
47+
Requires<[HasNontrappingFPToInt]>;
48+
def I64_TRUNC_S_SAT_F32 : I<(outs I64:$dst), (ins F32:$src),
49+
[(set I64:$dst, (fp_to_sint F32:$src))],
50+
"i64.trunc_s:sat/f32\t$dst, $src", 0xfc04>,
51+
Requires<[HasNontrappingFPToInt]>;
52+
def I64_TRUNC_U_SAT_F32 : I<(outs I64:$dst), (ins F32:$src),
53+
[(set I64:$dst, (fp_to_uint F32:$src))],
54+
"i64.trunc_u:sat/f32\t$dst, $src", 0xfc05>,
55+
Requires<[HasNontrappingFPToInt]>;
56+
def I32_TRUNC_S_SAT_F64 : I<(outs I32:$dst), (ins F64:$src),
57+
[(set I32:$dst, (fp_to_sint F64:$src))],
58+
"i32.trunc_s:sat/f64\t$dst, $src", 0xfc02>,
59+
Requires<[HasNontrappingFPToInt]>;
60+
def I32_TRUNC_U_SAT_F64 : I<(outs I32:$dst), (ins F64:$src),
61+
[(set I32:$dst, (fp_to_uint F64:$src))],
62+
"i32.trunc_u:sat/f64\t$dst, $src", 0xfc03>,
63+
Requires<[HasNontrappingFPToInt]>;
64+
def I64_TRUNC_S_SAT_F64 : I<(outs I64:$dst), (ins F64:$src),
65+
[(set I64:$dst, (fp_to_sint F64:$src))],
66+
"i64.trunc_s:sat/f64\t$dst, $src", 0xfc06>,
67+
Requires<[HasNontrappingFPToInt]>;
68+
def I64_TRUNC_U_SAT_F64 : I<(outs I64:$dst), (ins F64:$src),
69+
[(set I64:$dst, (fp_to_uint F64:$src))],
70+
"i64.trunc_u:sat/f64\t$dst, $src", 0xfc07>,
71+
Requires<[HasNontrappingFPToInt]>;
72+
73+
// Conversion from floating point to integer pseudo-instructions which don't
74+
// trap on overflow or invalid.
75+
let usesCustomInserter = 1, isCodeGenOnly = 1 in {
76+
def FP_TO_SINT_I32_F32 : I<(outs I32:$dst), (ins F32:$src),
77+
[(set I32:$dst, (fp_to_sint F32:$src))], "", 0>,
78+
Requires<[NotHasNontrappingFPToInt]>;
79+
def FP_TO_UINT_I32_F32 : I<(outs I32:$dst), (ins F32:$src),
80+
[(set I32:$dst, (fp_to_uint F32:$src))], "", 0>,
81+
Requires<[NotHasNontrappingFPToInt]>;
82+
def FP_TO_SINT_I64_F32 : I<(outs I64:$dst), (ins F32:$src),
83+
[(set I64:$dst, (fp_to_sint F32:$src))], "", 0>,
84+
Requires<[NotHasNontrappingFPToInt]>;
85+
def FP_TO_UINT_I64_F32 : I<(outs I64:$dst), (ins F32:$src),
86+
[(set I64:$dst, (fp_to_uint F32:$src))], "", 0>,
87+
Requires<[NotHasNontrappingFPToInt]>;
88+
def FP_TO_SINT_I32_F64 : I<(outs I32:$dst), (ins F64:$src),
89+
[(set I32:$dst, (fp_to_sint F64:$src))], "", 0>,
90+
Requires<[NotHasNontrappingFPToInt]>;
91+
def FP_TO_UINT_I32_F64 : I<(outs I32:$dst), (ins F64:$src),
92+
[(set I32:$dst, (fp_to_uint F64:$src))], "", 0>,
93+
Requires<[NotHasNontrappingFPToInt]>;
94+
def FP_TO_SINT_I64_F64 : I<(outs I64:$dst), (ins F64:$src),
95+
[(set I64:$dst, (fp_to_sint F64:$src))], "", 0>,
96+
Requires<[NotHasNontrappingFPToInt]>;
97+
def FP_TO_UINT_I64_F64 : I<(outs I64:$dst), (ins F64:$src),
98+
[(set I64:$dst, (fp_to_uint F64:$src))], "", 0>,
99+
Requires<[NotHasNontrappingFPToInt]>;
100+
} // usesCustomInserter, isCodeGenOnly = 1
101+
38102
// Conversion from floating point to integer traps on overflow and invalid.
39103
let hasSideEffects = 1 in {
40104
def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
41-
[(set I32:$dst, (fp_to_sint F32:$src))],
42-
"i32.trunc_s/f32\t$dst, $src", 0xa8>;
105+
[], "i32.trunc_s/f32\t$dst, $src", 0xa8>;
43106
def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
44-
[(set I32:$dst, (fp_to_uint F32:$src))],
45-
"i32.trunc_u/f32\t$dst, $src", 0xa9>;
107+
[], "i32.trunc_u/f32\t$dst, $src", 0xa9>;
46108
def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src),
47-
[(set I64:$dst, (fp_to_sint F32:$src))],
48-
"i64.trunc_s/f32\t$dst, $src", 0xae>;
109+
[], "i64.trunc_s/f32\t$dst, $src", 0xae>;
49110
def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src),
50-
[(set I64:$dst, (fp_to_uint F32:$src))],
51-
"i64.trunc_u/f32\t$dst, $src", 0xaf>;
111+
[], "i64.trunc_u/f32\t$dst, $src", 0xaf>;
52112
def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src),
53-
[(set I32:$dst, (fp_to_sint F64:$src))],
54-
"i32.trunc_s/f64\t$dst, $src", 0xaa>;
113+
[], "i32.trunc_s/f64\t$dst, $src", 0xaa>;
55114
def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src),
56-
[(set I32:$dst, (fp_to_uint F64:$src))],
57-
"i32.trunc_u/f64\t$dst, $src", 0xab>;
115+
[], "i32.trunc_u/f64\t$dst, $src", 0xab>;
58116
def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src),
59-
[(set I64:$dst, (fp_to_sint F64:$src))],
60-
"i64.trunc_s/f64\t$dst, $src", 0xb0>;
117+
[], "i64.trunc_s/f64\t$dst, $src", 0xb0>;
61118
def I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src),
62-
[(set I64:$dst, (fp_to_uint F64:$src))],
63-
"i64.trunc_u/f64\t$dst, $src", 0xb1>;
119+
[], "i64.trunc_u/f64\t$dst, $src", 0xb1>;
64120
} // hasSideEffects = 1
65121

66122
def F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src),

‎lib/Target/WebAssembly/WebAssemblyInstrInfo.td

+8
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,14 @@ def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
2020
def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
2121
def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
2222
AssemblerPredicate<"FeatureSIMD128", "simd128">;
23+
def HasNontrappingFPToInt :
24+
Predicate<"Subtarget->hasNontrappingFPToInt()">,
25+
AssemblerPredicate<"FeatureNontrappingFPToInt",
26+
"nontrapping-fptoint">;
27+
def NotHasNontrappingFPToInt :
28+
Predicate<"!Subtarget->hasNontrappingFPToInt()">,
29+
AssemblerPredicate<"!FeatureNontrappingFPToInt",
30+
"nontrapping-fptoint">;
2331

2432
//===----------------------------------------------------------------------===//
2533
// WebAssembly-specific DAG Node Types.

‎lib/Target/WebAssembly/WebAssemblySubtarget.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
4141
const std::string &FS,
4242
const TargetMachine &TM)
4343
: WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
44-
CPUString(CPU), TargetTriple(TT), FrameLowering(),
44+
HasNontrappingFPToInt(false), CPUString(CPU),
45+
TargetTriple(TT), FrameLowering(),
4546
InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
4647
TLInfo(TM, *this) {}
4748

‎lib/Target/WebAssembly/WebAssemblySubtarget.h

+2
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ namespace llvm {
3030

3131
class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
3232
bool HasSIMD128;
33+
bool HasNontrappingFPToInt;
3334

3435
/// String name of used CPU.
3536
std::string CPUString;
@@ -74,6 +75,7 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
7475
// Predicates used by WebAssemblyInstrInfo.td.
7576
bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
7677
bool hasSIMD128() const { return HasSIMD128; }
78+
bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
7779

7880
/// Parses features string setting specified subtarget options. Definition of
7981
/// function is auto generated by tblgen.

0 commit comments

Comments
 (0)