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[SOL] Remove lddw instruction (llvm#74)
* Remove lddw instruction * Add suggestions
1 parent 11865e1 commit 2885985

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10 files changed

+153
-53
lines changed

10 files changed

+153
-53
lines changed

‎llvm/lib/Target/SBF/MCTargetDesc/SBFMCCodeEmitter.cpp

+8-4
Original file line numberDiff line numberDiff line change
@@ -93,17 +93,21 @@ unsigned SBFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
9393
if (MI.getOpcode() == SBF::JAL)
9494
// func call name
9595
Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4));
96-
else if (MI.getOpcode() == SBF::LD_imm64)
96+
else if (MI.getOpcode() == SBF::LD_imm64 ||
97+
MI.getOpcode() == SBF::MOV_32_64_addr)
9798
Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
98-
else
99+
// In SBFv2, LD_imm64 is replaced by MOV_32_64_addr and HOR_addr when loading
100+
// addresses. These two instructions always appear together, so if a
101+
// relocation is necessary, we only insert it for one of them, in this case
102+
// MOV_32_64.
103+
else if (MI.getOpcode() != SBF::HOR_addr)
99104
// bb label
100105
Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
101106

102107
return 0;
103108
}
104109

105-
static uint8_t SwapBits(uint8_t Val)
106-
{
110+
static uint8_t SwapBits(uint8_t Val) {
107111
return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
108112
}
109113

‎llvm/lib/Target/SBF/SBFInstrFormats.td

+1
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@ def SBF_MOV : SBFArithOp<0xb>;
4444
def SBF_ARSH : SBFArithOp<0xc>;
4545
def SBF_END : SBFArithOp<0xd>;
4646
def SBF_SDIV : SBFArithOp<0xe>;
47+
def SBF_HOR : SBFArithOp<0xf>;
4748

4849
def SBF_XCHG : SBFArithOp<0xe>;
4950
def SBF_CMPXCHG : SBFArithOp<0xf>;

‎llvm/lib/Target/SBF/SBFInstrInfo.td

+56-4
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,21 @@ def i64immSExt32 : PatLeaf<(i64 imm),
7171
def i32immSExt32 : PatLeaf<(i32 imm),
7272
[{return isInt<32>(N->getSExtValue()); }]>;
7373

74+
// Fetch the upper 32-bits of a 64-bit integer.
75+
def Upper32 : SDNodeXForm<imm, [{
76+
uint64_t value = N->getSExtValue() >> 32;
77+
return CurDAG->getTargetConstant(value, SDLoc(N),
78+
N->getValueType(0));
79+
}]>;
80+
81+
// Fetch the lower 32-bits of a 64-bit integer.
82+
def Lower32 : SDNodeXForm<imm, [{
83+
uint64_t value = N->getSExtValue() & 0x00000000ffffffff;
84+
return CurDAG->getTargetConstant(value, SDLoc(N),
85+
N->getValueType(0));
86+
}]>;
87+
88+
7489
// Addressing modes.
7590
def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
7691
def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
@@ -302,6 +317,22 @@ let Constraints = "$dst = $src2" in {
302317
defm SRL : ALU<SBF_RSH, "rsh", srl>;
303318
defm XOR : ALU<SBF_XOR, "xor", xor>;
304319
defm SRA : ALU<SBF_ARSH, "arsh", sra>;
320+
321+
let Predicates = [SBFv2] in {
322+
def HOR : ALU_RI<SBF_ALU64, SBF_HOR,
323+
(outs GPR:$dst),
324+
(ins GPR:$src2, i32imm:$imm),
325+
"hor64 $dst, $imm",
326+
[]>;
327+
let DecoderNamespace = "AddrLoad" in {
328+
def HOR_addr : ALU_RI<SBF_ALU64, SBF_HOR,
329+
(outs GPR:$dst),
330+
(ins GPR:$src2, u64imm:$imm),
331+
"hor64 $dst, $imm",
332+
[]>;
333+
334+
}
335+
}
305336
}
306337

307338
defm MUL : ALU<SBF_MUL, "mul", mul>;
@@ -370,7 +401,7 @@ class LD_IMM64<bits<4> Pseudo, string Mnemonic>
370401
}
371402

372403
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
373-
def LD_imm64 : LD_IMM64<0, "lddw">;
404+
def LD_imm64 : LD_IMM64<0, "lddw">, Requires<[NoSBFv2]>;
374405
def MOV_rr : ALU_RR<SBF_ALU64, SBF_MOV,
375406
(outs GPR:$dst),
376407
(ins GPR:$src),
@@ -632,9 +663,6 @@ let usesCustomInserter = 1, isCodeGenOnly = 1 in {
632663
(SBFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>;
633664
}
634665

635-
// load 64-bit global addr into register
636-
def : Pat<(SBFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
637-
638666
// 0xffffFFFF doesn't fit into simm32, optimize common case
639667
def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
640668
(SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
@@ -902,8 +930,32 @@ let isCodeGenOnly = 1 in {
902930
def MOV_32_64 : ALU_RR<SBF_ALU, SBF_MOV,
903931
(outs GPR:$dst), (ins GPR32:$src),
904932
"mov32 $dst, $src", []>;
933+
let Predicates = [SBFv2] in {
934+
def MOV_32_64_imm : ALU_RI<SBF_ALU, SBF_MOV,
935+
(outs GPR:$dst), (ins i32imm:$imm),
936+
"mov32 $dst, $imm", []>;
937+
def MOV_32_64_addr : ALU_RI<SBF_ALU, SBF_MOV,
938+
(outs GPR:$dst), (ins u64imm:$imm),
939+
"mov32 $dst, $imm", []>;
940+
}
905941
}
906942

943+
// In SBFv2, a CopyToReg of a 64-bit value is split in two instructions:
944+
// mov32 r1, 0x55667788
945+
// hor r1, 0x11223344
946+
// These instructions copy the value 0x1122334455667788 to a register.
947+
def : Pat<(i64 imm:$imm),
948+
(HOR (MOV_32_64_imm (i32 (Lower32 $imm))),
949+
(i32 (Upper32 $imm)))>, Requires<[SBFv2]>;
950+
951+
// load 64-bit global address into register.
952+
def : Pat<(SBFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>,
953+
Requires<[NoSBFv2]>;
954+
def : Pat<(SBFWrapper tglobaladdr:$in),
955+
(HOR_addr (MOV_32_64_addr tglobaladdr:$in),
956+
tglobaladdr:$in)>, Requires<[SBFv2]>;
957+
958+
907959
def : Pat<(i64 (sext GPR32:$src)),
908960
(SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
909961

‎llvm/test/CodeGen/SBF/cc_args.ll

+52-36
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,52 @@
1-
; RUN: llc < %s -march=sbf -show-mc-encoding | FileCheck %s
1+
; RUN: llc < %s -march=sbf -show-mc-encoding | FileCheck --check-prefix=CHECK-v1 %s
2+
; RUN: llc < %s -march=sbf -mcpu=sbfv2 -show-mc-encoding | FileCheck --check-prefix=CHECK-v2 %s
23

34
define void @test() #0 {
45
entry:
5-
; CHECK: test:
6+
; CHECK-LABEL: test:
67

7-
; CHECK: mov64 r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
8-
; CHECK: call f_i16
8+
; CHECK-v1: mov64 r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
9+
; CHECK-v2: mov64 r1, 123
10+
; CHECK-v1: call f_i16
911
call void @f_i16(i16 123)
1012

11-
; CHECK: mov64 r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
12-
; CHECK: call f_i32
13+
; CHECK-v1: mov64 r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
14+
; CHECK-v2: mov64 r1, 12345678
15+
; CHECK-v1: call f_i32
1316
call void @f_i32(i32 12345678)
1417

15-
; CHECK: lddw r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
16-
; CHECK: call f_i64
18+
; 72623859790382856 = 0x0102030405060708
19+
; 84281096 = 0x05060708
20+
; 16909060 = 0x01020304
21+
22+
; CHECK-v2: mov32 r1, 84281096 # encoding: [0xb4,0x01,0x00,0x00,0x08,0x07,0x06,0x05]
23+
; CHECK-v2: hor64 r1, 16909060 # encoding: [0xf7,0x01,0x00,0x00,0x04,0x03,0x02,0x01]
24+
25+
; CHECK-v1: lddw r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
26+
; CHECK-v1: call f_i64
1727
call void @f_i64(i64 72623859790382856)
1828

19-
; CHECK: mov64 r1, 1234
20-
; CHECK: mov64 r2, 5678
21-
; CHECK: call f_i32_i32
29+
; CHECK-v1: mov64 r1, 1234
30+
; CHECK-v1: mov64 r2, 5678
31+
; CHECK-v1: call f_i32_i32
2232
call void @f_i32_i32(i32 1234, i32 5678)
2333

24-
; CHECK: mov64 r1, 2
25-
; CHECK: mov64 r2, 3
26-
; CHECK: mov64 r3, 4
27-
; CHECK: call f_i16_i32_i16
34+
; CHECK-v1: mov64 r1, 2
35+
; CHECK-v1: mov64 r2, 3
36+
; CHECK-v1: mov64 r3, 4
37+
; CHECK-v1: call f_i16_i32_i16
2838
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
2939

30-
; CHECK: mov64 r1, 5
31-
; CHECK: lddw r2, 7262385979038285
32-
; CHECK: mov64 r3, 6
33-
; CHECK: call f_i16_i64_i16
40+
; 7262385979038285 = 0x0019CD1A00809A4D
41+
; 8428109 = 0x00809A4D
42+
; 1690906 = 0x0019CD1A
43+
; CHECK-v2: mov32 r2, 8428109
44+
; CHECK-v2: hor64 r2, 1690906
45+
46+
; CHECK-v1: mov64 r1, 5
47+
; CHECK-v1: lddw r2, 7262385979038285
48+
; CHECK-v1: mov64 r3, 6
49+
; CHECK-v1: call f_i16_i64_i16
3450
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
3551

3652
ret void
@@ -41,53 +57,53 @@ entry:
4157
@g_i64 = common global i64 0, align 4
4258

4359
define void @f_i16(i16 %a) #0 {
44-
; CHECK: f_i16:
45-
; CHECK: stxh [r2 + 0], r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
60+
; CHECK-v1: f_i16:
61+
; CHECK-v1: stxh [r2 + 0], r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
4662
store volatile i16 %a, i16* @g_i16, align 2
4763
ret void
4864
}
4965

5066
define void @f_i32(i32 %a) #0 {
51-
; CHECK: f_i32:
52-
; CHECK: stxw [r2 + 0], r1 # encoding: [0x63,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
67+
; CHECK-v1: f_i32:
68+
; CHECK-v1: stxw [r2 + 0], r1 # encoding: [0x63,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
5369
store volatile i32 %a, i32* @g_i32, align 2
5470
ret void
5571
}
5672

5773
define void @f_i64(i64 %a) #0 {
58-
; CHECK: f_i64:
59-
; CHECK: stxdw [r2 + 0], r1 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
74+
; CHECK-v1: f_i64:
75+
; CHECK-v1: stxdw [r2 + 0], r1 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
6076
store volatile i64 %a, i64* @g_i64, align 2
6177
ret void
6278
}
6379

6480
define void @f_i32_i32(i32 %a, i32 %b) #0 {
65-
; CHECK: f_i32_i32:
66-
; CHECK: stxw [r3 + 0], r1
81+
; CHECK-v1: f_i32_i32:
82+
; CHECK-v1: stxw [r3 + 0], r1
6783
store volatile i32 %a, i32* @g_i32, align 4
68-
; CHECK: stxw [r3 + 0], r2
84+
; CHECK-v1: stxw [r3 + 0], r2
6985
store volatile i32 %b, i32* @g_i32, align 4
7086
ret void
7187
}
7288

7389
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
74-
; CHECK: f_i16_i32_i16:
75-
; CHECK: stxh [r4 + 0], r1
90+
; CHECK-v1: f_i16_i32_i16:
91+
; CHECK-v1: stxh [r4 + 0], r1
7692
store volatile i16 %a, i16* @g_i16, align 2
77-
; CHECK: stxw [r1 + 0], r2
93+
; CHECK-v1: stxw [r1 + 0], r2
7894
store volatile i32 %b, i32* @g_i32, align 4
79-
; CHECK: stxh [r4 + 0], r3
95+
; CHECK-v1: stxh [r4 + 0], r3
8096
store volatile i16 %c, i16* @g_i16, align 2
8197
ret void
8298
}
8399

84100
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
85-
; CHECK: f_i16_i64_i16:
86-
; CHECK: stxh [r4 + 0], r1
101+
; CHECK-v1: f_i16_i64_i16:
102+
; CHECK-v1: stxh [r4 + 0], r1
87103
store volatile i16 %a, i16* @g_i16, align 2
88-
; CHECK: stxdw [r1 + 0], r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
104+
; CHECK-v1: stxdw [r1 + 0], r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
89105
store volatile i64 %b, i64* @g_i64, align 8
90-
; CHECK: stxh [r4 + 0], r3
106+
; CHECK-v1: stxh [r4 + 0], r3
91107
store volatile i16 %c, i16* @g_i16, align 2
92108
ret void
93109
}

‎llvm/test/CodeGen/SBF/objdump_cond_op.ll

+6-3
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,8 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
3434
%10 = load i32, i32* @gbl, align 4
3535
br i1 %9, label %15, label %11
3636

37-
; CHECK: lddw r1, 0x0
37+
; CHECK: mov32 w1, 0x0
38+
; CHECK: hor64 r1, 0x0
3839
; CHECK: ldxw r0, [r1 + 0x0]
3940
; CHECK: mul64 r0, r0
4041
; CHECK: lsh64 r0, 0x1
@@ -45,7 +46,8 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
4546
br label %13
4647

4748
; CHECK-LABEL: <LBB0_2>:
48-
; CHECK: lddw r3, 0x0
49+
; CHECK: mov32 w3, 0x0
50+
; CHECK: hor64 r3, 0x0
4951
; CHECK: ldxw r0, [r3 + 0x0]
5052
; CHECK: lsh64 r2, 0x20
5153
; CHECK: rsh64 r2, 0x20
@@ -57,7 +59,8 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
5759
store i32 %14, i32* @gbl, align 4
5860
br label %15
5961
; CHECK-LABEL: <LBB0_4>:
60-
; CHECK: lddw r1, 0x0
62+
; CHECK: mov32 w1, 0x0
63+
; CHECK: hor64 r1, 0x0
6164
; CHECK: stxw [r1 + 0x0], r0
6265

6366
; <label>:15: ; preds = %8, %13

‎llvm/test/CodeGen/SBF/objdump_imm_hex.ll

+19-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; RUN: llc -march=sbf -mcpu=sbfv2 -filetype=obj -o - %s | llvm-objdump -d - | FileCheck --check-prefix=CHECK-DEC %s
22
; RUN: llc -march=sbf -mcpu=sbfv2 -filetype=obj -o - %s | llvm-objdump -d --print-imm-hex - | FileCheck --check-prefix=CHECK-HEX %s
3+
; RUN: llc < %s -march=sbf -mcpu=sbfv2 -show-mc-encoding | FileCheck --check-prefix=CHECK-REL %s
34

45
; Source Code:
56
; int gbl;
@@ -25,12 +26,19 @@ define i32 @test(i64, i64) local_unnamed_addr #0 {
2526
; CHECK-LABEL: test
2627
%3 = icmp eq i64 %0, -6067004223159161907
2728
br i1 %3, label %4, label %8
28-
; CHECK-DEC: 18 03 00 00 cd ab cd ab 00 00 00 00 cd ab cd ab lddw r3, -0x5432543254325433
29+
; CHECK-DEC: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433
30+
; CHECK-DEC: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433
2931
; CHECK-DEC: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7
30-
; CHECK-HEX: 18 03 00 00 cd ab cd ab 00 00 00 00 cd ab cd ab lddw r3, -0x5432543254325433
32+
; CHECK-HEX: b4 03 00 00 cd ab cd ab mov32 w3, -0x54325433
33+
; CHECK-HEX: f7 03 00 00 cd ab cd ab hor64 r3, -0x54325433
3134
; CHECK-HEX: 5d 31 07 00 00 00 00 00 jne r1, r3, +0x7
3235

3336
; <label>:4: ; preds = %2
37+
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
38+
; CHECK-DEC: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
39+
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
40+
; CHECK-HEX: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
41+
; CHECK-REL: fixup A - offset: 0, value: gbl, kind: FK_SecRel_8
3442
%5 = load i32, i32* @gbl, align 4
3543
%6 = shl i32 %5, 1
3644
; CHECK-DEC: 67 01 00 00 01 00 00 00 lsh64 r1, 0x1
@@ -40,11 +48,18 @@ define i32 @test(i64, i64) local_unnamed_addr #0 {
4048

4149
; <label>:8: ; preds = %2
4250
%9 = icmp eq i64 %1, 188899839028173
43-
; CHECK-DEC: 18 01 00 00 cd ab cd ab 00 00 00 00 cd ab 00 00 lddw r1, 0xabcdabcdabcd
44-
; CHECK-HEX: 18 01 00 00 cd ab cd ab 00 00 00 00 cd ab 00 00 lddw r1, 0xabcdabcdabcd
51+
; CHECK-DEC: b4 01 00 00 cd ab cd ab mov32 w1, -0x54325433
52+
; CHECK-DEC: f7 01 00 00 cd ab 00 00 hor64 r1, 0xabcd
53+
; CHECK-HEX: b4 01 00 00 cd ab cd ab mov32 w1, -0x54325433
54+
; CHECK-HEX: f7 01 00 00 cd ab 00 00 hor64 r1, 0xabcd
4555
br i1 %9, label %10, label %16
4656

4757
; <label>:10: ; preds = %8
58+
; CHECK-DEC: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
59+
; CHECK-DEC: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
60+
; CHECK-HEX: b4 01 00 00 00 00 00 00 mov32 w1, 0x0
61+
; CHECK-HEX: f7 01 00 00 00 00 00 00 hor64 r1, 0x0
62+
; CHECK-REL: fixup A - offset: 0, value: gbl, kind: FK_SecRel_8
4863
%11 = load i32, i32* @gbl, align 4
4964
%12 = shl nsw i32 %11, 2
5065
br label %13

‎llvm/test/CodeGen/SBF/objdump_static_var.ll

+4-2
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,14 @@
1010
; Function Attrs: norecurse nounwind
1111
define dso_local i32 @test() local_unnamed_addr #0 {
1212
%1 = load volatile i64, i64* @a, align 8, !tbaa !2
13-
; CHECK: lddw r1, 0x0
13+
; CHECK: mov32 w1, 0x0
1414
; CHECK: R_SBF_64_64 a
15+
; CHECK: hor64 r1, 0x0
1516
; CHECK: ldxdw r1, [r1 + 0x0]
1617
%2 = load volatile i32, i32* @b, align 4, !tbaa !6
17-
; CHECK: lddw r2, 0x0
18+
; CHECK: mov32 w2, 0x0
1819
; CHECK: R_SBF_64_64 b
20+
; CHECK: hor64 r2, 0x0
1921
; CHECK: ldxw r0, [r2 + 0x0]
2022
%3 = trunc i64 %1 to i32
2123
%4 = add i32 %2, %3

‎llvm/test/MC/Disassembler/SBF/sbf-alu.txt

+2
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,8 @@
102102
0xe4,0x05,0x00,0x00,0x85,0xff,0xff,0xff
103103

104104

105+
# CHECK-NEW: hor64 r0, 129
106+
0xf7,0x90,0x00,0x00,0x81,0x00,0x00,0x00
105107

106108
# CHECK-NEW: or64 r0, r9
107109
0x4f,0x90,0x00,0x00,0x00,0x00,0x00,0x00

‎llvm/test/MC/SBF/insn-unit.s

+2
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,7 @@ Llabel0 :
149149
mov64 r9, 1 // BPF_MOV | BPF_K
150150
mov64 r9, 0xffffffff // BPF_MOV | BPF_K
151151
arsh64 r10, 64 // BPF_ARSH | BPF_K
152+
hor64 r3, 0xcafe // SBF_HOR
152153
// CHECK: 47 04 00 00 ff 00 00 00 or64 r4, 0xff
153154
// CHECK: 57 05 00 00 ff 00 00 00 and64 r5, 0xff
154155
// CHECK: 67 06 00 00 3f 00 00 00 lsh64 r6, 0x3f
@@ -157,3 +158,4 @@ Llabel0 :
157158
// CHECK: b7 09 00 00 01 00 00 00 mov64 r9, 0x1
158159
// CHECK: b7 09 00 00 ff ff ff ff mov64 r9, -0x1
159160
// CHECK: c7 0a 00 00 40 00 00 00 arsh64 r10, 0x40
161+
// CHECK: f7 03 00 00 fe ca 00 00 hor64 r3, 0xcafe

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