Skip to content

Commit e77d593

Browse files
authored
Rollup merge of rust-lang#91608 - workingjubilee:fold-neon-fp, r=Amanieu
Fold aarch64 feature +fp into +neon Arm's FEAT_FP and Feat_AdvSIMD describe the same thing on AArch64: The Neon unit, which handles both floating point and SIMD instructions. Moreover, a configuration for AArch64 must include both or neither. Arm says "entirely proprietary" toolchains may omit floating point: https://developer.arm.com/documentation/102374/0101/Data-processing---floating-point In the Programmer's Guide for Armv8-A, Arm says AArch64 can have both FP and Neon or neither in custom implementations: https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON In "Bare metal boot code for Armv8-A", enabling Neon and FP is just disabling the same trap flag: https://developer.arm.com/documentation/dai0527/a In an unlikely future where "Neon and FP" become unrelated, we can add "[+-]fp" as its own feature flag. Until then, we can simplify programming with Rust on AArch64 by folding both into "[+-]neon", which is valid as it supersets both. "[+-]neon" is retained for niche uses such as firmware, kernels, "I just hate floats", and so on. I am... pretty sure no one is relying on this. An argument could be made that, as we are not an "entirely proprietary" toolchain, we should not support AArch64 without floats at all. I think that's a bit excessive. However, I want to recognize the intent: programming for AArch64 should be simplified where possible. For x86-64, programmers regularly set up illegal feature configurations because it's hard to understand them, see rust-lang#89586. And per the above notes, plus the discussion in rust-lang#86941, there should be no real use cases for leaving these features split: the two should in fact always go together. Fixes rust-lang#95002. Fixes rust-lang#95122.
2 parents 3ea4493 + f4e7fde commit e77d593

File tree

3 files changed

+6
-10
lines changed

3 files changed

+6
-10
lines changed

compiler/rustc_codegen_llvm/src/llvm_util.rs

+4-6
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,6 @@ pub fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> SmallVec<[&'a str; 2]
187187
("x86", "avx512vaes") => smallvec!["vaes"],
188188
("x86", "avx512gfni") => smallvec!["gfni"],
189189
("x86", "avx512vpclmulqdq") => smallvec!["vpclmulqdq"],
190-
("aarch64", "fp") => smallvec!["fp-armv8"],
191190
("aarch64", "rcpc2") => smallvec!["rcpc-immo"],
192191
("aarch64", "dpb") => smallvec!["ccpp"],
193192
("aarch64", "dpb2") => smallvec!["ccdp"],
@@ -238,12 +237,11 @@ pub fn target_features(sess: &Session) -> Vec<Symbol> {
238237
.filter_map(|&(feature, gate)| {
239238
if sess.is_nightly_build() || gate.is_none() { Some(feature) } else { None }
240239
})
240+
.flat_map(|feature| to_llvm_features(sess, feature))
241241
.filter(|feature| {
242-
for llvm_feature in to_llvm_features(sess, feature) {
243-
let cstr = SmallCStr::new(llvm_feature);
244-
if unsafe { llvm::LLVMRustHasFeature(target_machine, cstr.as_ptr()) } {
245-
return true;
246-
}
242+
let cstr = SmallCStr::new(feature);
243+
if unsafe { llvm::LLVMRustHasFeature(target_machine, cstr.as_ptr()) } {
244+
return true;
247245
}
248246
false
249247
})

compiler/rustc_codegen_ssa/src/target_features.rs

+1-3
Original file line numberDiff line numberDiff line change
@@ -43,10 +43,8 @@ const ARM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
4343
];
4444

4545
const AARCH64_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
46-
// FEAT_AdvSimd
46+
// FEAT_AdvSimd & FEAT_FP
4747
("neon", None),
48-
// FEAT_FP
49-
("fp", None),
5048
// FEAT_FP16
5149
("fp16", None),
5250
// FEAT_SVE

compiler/rustc_target/src/asm/aarch64.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ impl AArch64InlineAsmRegClass {
6464
match self {
6565
Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
6666
Self::vreg | Self::vreg_low16 => types! {
67-
fp: I8, I16, I32, I64, F32, F64,
67+
neon: I8, I16, I32, I64, F32, F64,
6868
VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2), VecF64(1),
6969
VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
7070
},

0 commit comments

Comments
 (0)